WM2636 12-bit serial input voltage output dac with internal reference production data, july 1999, rev 1.0 wolfson microelectronics ltd lutton court, bernard terrace, edinburgh, eh8 9nx, uk tel: +44 (0) 131 667 9386 fax: +44 (0) 131 667 5176 email: sales@wolfson.co.uk http://www.wolfson.co.uk production data contain final specifications current on publication date. supply of products conforms to wolfson microelectronics? terms and conditions. ? 1999 wolfson microelectronics ltd . features ? 12-bit voltage output dac ? single supply from 2.7v to 5.5v ? dnl 0.5 lsbs, inl 2.0 lsbs ? very low power consumption (3v supply): - 4.2mw, slow mode - 8.1mw, fast mode ? tms320, (q)spi ? , and microwire ? compatible serial interface ? programmable settling time of 3.5 s or 1 s typical ? high impedance reference input buffer ? power down mode 10na applications ? battery powered test instruments ? digital offset and gain adjustment ? battery operated/remote industrial controls ? machine and motion control devices ? wireless telephone and communication systems ? speech synthesis ? arbitrary waveform generation ordering information device temp. range package WM2636cd 0 to 70 c 8-pin soic WM2636id -40 to 85 c 8-pin soic description the WM2636 is a 12-bit voltage output, resistor string digital-to- analogue converter that can be powered down under software control. power down reduces current consumption to 10na. an internal precision voltage reference is provided which can source up to 1ma. this can therefore be used as an external system reference. the device has been designed to interface efficiently to industry standard microprocessors and dsps, including the tms320 family. the WM2636 is programmed with a 16-bit serial word comprising 4 control bits and 12 data bits. excellent performance is delivered with a typical dnl of 0.5 lsbs. the settling time of the dac is programmable to allow the designer to optimize speed versus power dissipation. the output stage is buffered by a x2 gain near rail-to-rail amplifier. the device is available in an 8-pin soic package. commercial temperature (0 to 70 c) and industrial temperature (-40 to 85 c) variants are supported. block diagram typical performance (7) out 12-bit dac latch power-on reset din (1) sclk (2) fs (4) (5) agnd vdd (8) powerdown/ speed control 2-bit control latch reference input buffer 16-bit shift register and control logic data x1 x2 dac output buffer ncs (3) 2-bit reference select latch 1.024v/2.048v selectable reference x1 reference output buffer with ouput enable ref(6) WM2636 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 512 1024 1536 2048 2559 3071 3583 4095 digital code dnl - lsb vdd = 5v, v ref = external, speed = fast mode, load = 10k/100pf
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 2 pin configuration 1 2 3 4 ncs din sclk agnd ref fs vdd out 5 6 7 8 pin description pin no name type description 1 din digital input serial data input. 2 sclk digital input serial clock input. 3 ncs digital input chip select. this pin is active low. 4 fs digital input frame synchronisation for serial input data. 5 agnd supply analogue ground. 6 ref analogue i/o analogue reference voltage input/output. 7 out analogue output dac analogue output 8 vdd supply positive power supply. absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. condition min max supply voltage, vdd to agnd 7v digital input voltage -0.3v vdd + 0.3v reference input voltage -0.3v vdd + 0.3v operating temperature range, t a WM2636cd WM2636id 0 c -40 c 70 c 85 c storage temperature -65 c 150 c lead temperature 1.6mm (1/16 inch) soldering for 10 seconds 260 c recommended operating conditions parameter symbol test conditions min typ max unit supply voltage vdd 2.7 5.5 v high-level digital input voltage v ih vdd = 2.7v to 5.5v 2 v low-level digital input voltage v il vdd = 2.7v to 5.5v 0.8 v reference voltage to ref v ref see note vdd - 1.5 v load resistance r l 210 k ? load capacitance c l 100 pf serial clock rate f sclk 20 mhz WM2636cd 0 70 c operating free-air temperature t a WM2636id -40 85 c note: reference voltages greater than vdd/2 will cause saturation for large dac codes.
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 3 electrical characteristics test conditions: r l = 10k ? , c l = 100pf. vdd = 5v 10%, v ref = 2.048v and vdd = 3v 10%, v ref = 1.024v over recommended operating free-air temperature range (unless noted otherwise). parameter symbol test conditions min typ max unit static dac specifications resolution 12 bits integral non-linearity inl see note 1 2.0 4.0 lsb differential non-linearity dnl see note 2 0.5 1.0 lsb zero code error zce see note 3 20 mv gain error ge see note 4 0.6 % fsr d.c. power supply rejection ratio dc psrr see note 5 0.5 mv/v zero code error temperature coefficient see note 6 10 ppm/ c gain error temperature coefficient see note 6 10 ppm/ c dac output specifications output voltage range 0 vdd - 0.1 v output load regulation 2k ? to 10k ? load see note 7 0.1 0.25 % power supplies no load, v ih = vdd, v il = 0v vdd = 5v, v ref = 2.048v slow 1.6 1.9 ma vdd = 5v, v ref = 2.048v fast 2.9 3.4 ma vdd = 3v, v ref = 1.024v slow 1.4 ma active supply current i dd vdd = 3v, v ref = 1.024v fast see note 8 2.7 ma power down supply current no load, all digital inputs 0v or vdd see note 9 0.01 10 a dynamic dac specifications slew rate dac code 128 to 4095, 10%-90% see note 10 slow fast 2 14 v/ s v/ s settling time dac code 128 to 4095 see note 11 slow fast 3.5 1.0 s s glitch energy code 2047 to 2048 10 nv-s signal to noise ratio snr fs = 400ksps, f out = 1khz, bw = 20khz see note 12 71 75 db signal to noise and distortion ratio snrd fs = 400ksps, f out = 1khz, bw = 20khz see note 12 59 66 db total harmonic distortion thd fs = 400ksps, f out = 1khz, bw = 20khz see note 12 -67 -59 db spurious free dynamic range spfdr fs = 400ksps, f out = 1khz, bw = 20khz see note 12 59 69 db
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 4 test conditions: r l = 10k ? , c l = 100pf. vdd = 5v 10%, v ref = 2.048v and vdd = 3v 10%, v ref = 1.024v over recommended operating free-air temperature range (unless noted otherwise). parameter symbol test conditions min typ max unit reference configured as input reference input resistance r refin 10 m ? reference input capacitance c refin 55 pf reference feedthrough v ref = 1v pp at 1khz + 1.024v dc, dac code 0 -65 db reference input bandwidth v ref = 0.2v pp + 1.024v dc dac code 2048 slow fast 1.0 1.0 mhz mhz reference configured as output low reference voltage v refoutl 1.003 1.024 1.045 v high reference voltage v refouth vdd > 4.75v 2.027 2.048 2.069 v output source current i refsrc 1ma output sink current i refsnk -1 ma load capacitance 100 pf psrr -48 db digital inputs high level input current i ih input voltage = vdd 1 a low level input current i il input voltage = 0v -1 a input capacitance c i 8pf notes: 1. integral non-linearity (inl) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. differential non-linearity (dnl) is the difference between the measured and ideal 1lsb amplitude change of any adjacent two codes. a guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. zero code error is the voltage output when the dac input code is zero. 4. gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. power supply rejection ratio is measured by varying vdd from 4.5v to 5.5v and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. zero code error and gain error temperature coefficients are normalised to full scale voltage. 7. output load regulation is the difference between the output voltage at full scale with a 10k ? load and 2k ? load. it is expressed as a percentage of the full scale output voltage with a 10k ? load. 8. i dd is measured while continuously writing code 2048 to the dac. for v ih < vdd - 0.7v and v il > 0.7v supply current will increase. 9. typical supply current in power down mode is 10na. production test limits are wider for speed of test. 10. slew rate results are for the lower value of the rising and falling edge slew rates 11. settling time is the time taken for the signal to settle to within 0.5lsb of the final measured value for both rising and falling edges. limits are ensured by design and characterisation, but are not production tested. 12. snr, snrd, thd and spfdr are measured on a synthesised sinewave at frequency f out generated with a sampling frequency fs .
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 5 serial interface * t suc16fs t sufs sclk din ncs fs 123451516 d0 d1 d12 d13 d14 d15 t wl t wh t sud t hd t sucsfs t whfs t suc16cs figure 1 timing diagram test conditions: r l = 10k ? , c l = 100pf. vdd = 5v 10%, v ref = 2.048v and vdd = 3v 10%, v ref = 1.024v over recommended operating free-air temperature range (unless noted otherwise). symbol test conditions min typ max unit t sucsfs setup time ncs low before negative fs edge. 10 ns t sufs setup time fs low before first negative sclk edge. 8ns t suc16fs setup time, sixteenth negative edge after fs low on which d0 is sampled before rising edge of fs. 10 ns t suc16cs setup time, sixteenth positive sclk edge (first positive after d0 sampled) before ncs rising edge. if fs is used instead of the sixteenth positive edge to update the dac, then the setup time is between the fs rising edge and the ncs rising edge. 10 ns t wh pulse duration, sclk high. 25 ns t wl pulse duration, sclk low. 25 ns t sud setup time, data ready before sclk falling edge. 8ns t hd hold time, data held valid after sclk falling edge. 5ns t whfs pulse duration, fs high. 20 ns
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 6 typical performance graphs vdd = 5v, v ref = external 2.048v, speed = fast mode -3 -2 -1 0 1 2 3 0 512 1024 1536 2048 2559 3071 3583 4095 digital code inl - lsb figure 2 integral non-linearity 0 0.5 1 1 .5 2 2.5 3 01233.54 i sink - ma output voltage - v s low fas t vdd = 3v, v r ef = 1v, input code = 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 00.511.522.533.54 isink - ma output voltage - v slow fast vdd = 5v, v ref = 2v, input code = 0 figure 3 sink current vdd = 3v figure 4 sink current vdd = 5v 2.066 2.0665 2.067 2.0675 2.068 2.0685 2.069 2.0695 2.07 2.0705 2.071 00.511.522.533.54 isource - ma output voltage - v slow fast vdd = 3v, v ref = 1v, input code = 4095 4.129 4.13 4.131 4.132 4.133 4.134 4.135 00.511.522.533.54 isource - ma output voltage - v slow fast vdd = 5v, v ref = 2v, input code = 4095 figure 5 source current vdd = 3v figure 6 source current vdd = 5v
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 7 device description general function the device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see block diagram). the output voltage is determined by the reference input voltage and the input code according to the following relationship: output voltage = () 4096 code v 2 ref input output 1111 1111 1111 () 4096 4095 v 2 ref :: 1000 0000 0001 () 4096 2049 v 2 ref 1000 0000 0000 () ref ref v 4096 2048 v 2 = 0111 1111 1111 () 4096 2047 v 2 ref :: 0000 0000 0001 () 4096 1 v 2 ref 0000 0000 0000 0v table 1 binary code table (0v to 2v ref output), gain = 2 power on reset an internal power-on-reset circuit resets the dac register to all 0s on power-up. buffer amplifier the output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k ? load with a 100pf load capacitance. serial interface explanation of data transfer: first, the device has to be enabled with ncs set to low. then, a falling edge of fs starts shifting the data bit-per-bit (starting with the msb) to the internal register on the falling edges of sclk. after 16 bits have been transferred or fs rises, the content of the shift register is moved to the dac latch which updates the voltage output to the new level. the serial interface of the device can be used in two basic modes: ? four wire (with chip select) ? three wire (without chip select) using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (dsp or microcontroller). if there is no need to have more than one device on the serial bus, then ncs can be tied low. serial clock and update rate figure 1 shows the device timing. the maximum serial rate is: f sclk max = mhz 20 t t 1 min wcl min wch = + the digital update rate is limited to an 800ns period, or 1.25mhz frequency. however, the dac settling time to 12 bits limits the update rate for large input step transitions.
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 8 software configuration options the 16 bits of data can be transferred with the sequence shown in table 2. d11-d0 contains the 12-bit data word. d15-d12 hold the programmable options. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r1 spd pwr r0 new dac or control register value (12 bits) table 2 serial word format programmable settling time settling time is a software selectable 3.5 s or 1 s, typical to within 0.5lsb of final value. this is controlled by the value of d14. a one defines a settling time of 1 s, a zero defines a settling time of 3.5 s. programmable power down the power down function is controlled by d13. a zero configures the device as active, or fully powered up, a one configures the device into power down mode. when the power down function is released the device reverts to the dac code set prior to power down. register addressing a separate internal control register is available. this is accessed from the register access bits r1 (bit d15) and r0 (bit d12). r1 (bit d15) r0 (bit d12) register 00 write data to dac 01 reserved 10 reserved 11 write data to control register table 3 register access control the contents of the control register, shown below in table 4, are used to program the internal reference function. d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxxxxref1ref0 table 4 control register contents programmable internal reference the reference can be sourced internally or externally under software control. if an external reference voltage is applied to the ref pin, the device must be configured to accept this. if an external reference is selected, the reference voltage input is buffered which makes the dac input resistance independent of code. the ref pin has an input resistance of 10m ? and an input capacitance of typically 55pf. the reference voltage determines the dac full-scale output. if an internal reference is selected, a voltage of 1.024v or 2.048 is available. the internal reference can source up to 1ma and can therefore be used as an external system reference. ref1 ref0) register 00 external 01 1.024v 10 2.048v 11 external table 5 programmable internal reference
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 9 examples: 1. set internal reference voltage to 2.048v d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1x01xxxxxxxxxx10 2. write new dac value and update dac output d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 x 0 0 new dac value
WM2636 production data wolfson microelectronics ltd pd rev 1.0 july 1999 10 package dimensions dm009.b d: 8 pin soic 3.9mm wide body symbols dimensions (mm) dimensions (inches) min max min max a 1.35 1.75 0.0532 0.0688 a 1 0.10 0.25 0.0040 0.0098 b 0.33 0.51 0.0130 0.0200 c 0.19 0.25 0.0075 0.0098 d 4.80 5.00 0.1890 0.1968 e 1.27 bsc 0.050 bsc e 3.80 4.00 0.1497 0.1574 h 0.25 0.50 0.0099 0.0196 h 5.80 6.20 0.2284 0.2440 l 0.40 1.27 0.0160 0.0500 0 o 8 o 0 o 8 o ref: jedec.95, ms-012 notes: a. all linear dimensions are in millimeters (inches). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm (0.010in). d. meets jedec.95 ms-012, variation = aa. refer to this specification for further details. c h x 45 o l a a1 seating plane -c- 0.10 (0.004) 4 1 d 5 8 e h b e
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